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ACD2203
CATV/TV/Video Downconverter with Dual Synthesizer
PRELIMINARY DATA SHEET - Rev 1.3
FEATURES
* * * * * * * * * * * Integrated Downconverter Integrated Dual Synthesizer 256 QAM Compatibility Single +5 V Power Supply Operation Low Power Consumption: <0.6 W Low Noise Figure: 8 dB High Conversion Gain: 10 dB Low Distortion: -53 dBc Two-Wire Interface Small Size -40 C to +85 C
APPLICATIONS
* * * * * Set Top Boxes CATV Video Tuners Digital TV Tuners CATV Data Tuners Cable Modems
S8 Package 28 Pin SSOP
PRODUCT DESCRIPTION
The ACD2203 uses both GaAs and Si technology to provide the downconverter and dual synthesizer functions in a double conversion tuner gain block, local oscillator, balanced mixer and dual synthesizer. The specifications meet the requirements of CATV/TV/Video and Cable Modem Data applications. The ACD2203 is supplied in a 28 lead SSOP package and requires a single +5 V supply voltage. The IC is well suited for applications where small size, low cost, low auxiliary parts count and a nocompromise performance is important. It provides for cost reduction by lowering the component and packaged IC count and decreasing the amount of labor-intensive production alignment steps, while significantly improving performance and reliability.
RFD
RF2: 64/65 Prescaler
18 Bit RF2 N Counter
RF2 Phase Detector
RF2 Charge Pump
CPD
RFIN+ RFINLow Noise VGA
VIF+IFOUT+
REFIN REFOUT
Oscillator
15 Bit RF2 R Counter
VIF+IFOUTMixer
RF1: 64/65 Prescaler
15 Bit RF1 R Counter
RFU
18 Bit RF1 N Counter
RF1 Phase Detector
RF1 Charge Pump
CPU
Phase Splitter
TCKT
OSC OUT
Clock Data AS
2 Bit A/D
24 Bit Data Register
Figure 1: Downconverter Block Diagram
12/2003
Figure 2: Dual Synthesizer Block Diagram
ACD2203
Figure 3: Pinout
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PRELIMINARY DATA SHEET - Rev 1.3 12/2003
ACD2203 Table 1: Pin Description
PIN
NAME
DESCRIPTION Downconverter Differential RFInput
PIN
NAME
DESCRIPTION Downconverter Differential IFOutput Inductively coupled to +VDD Downconverter Differential IFOutput Inductively coupled to +VDD Downconverter Ground (Must be connected) Oscillator and Phase Splitter Supply (+VDD) Oscillator Output (Connected to Synthesizer RF Input) Downconverter Ground (Must be connected) Downconverter Ground (Must be connected) Synthesizer Ground (Required) Synthesizer Ground (Required) Synthesizer Downconverter RFInput Synthesizer Downconverter Charge Pump Output Synthesizer Upconverter Charge Pump Output Synthesizer Upconverter RFInput Synthesizer Supply (+VDD)
1
RFIN+
28
VIF+IFOUT+
2
RFIN-
Downconverter Differential RFInput Downconverter Ground (Must be connected) Downconverter Gilbert Cell Current Source Resistor Oscillator Input Port (Tank circuit connection) Oscillator Tank Circuit Ground (Not to be connected to any other circuit ground) Same as Pin 6 Synthesizer Ground (Required) Synthesizer Ground (Required) Address Select
27
VIF+IFOUT -
3
GND
26
GND
4
ISET
25
VSUP
5
TCKT
24
OSCOUT
6
OSCGND
23
GND
7 8 9 10
OSCGND V SS V SS AS
22 21 20 19
GND V SS V SS RFD
11
DATA
2-Wire Interface Data
18
C PD
12 13
C LK REFIN
2-Wire Interface Clock Crystal Reference Input
17 16
C PU RFU
14
REFOUT
Crystal Reference Output
15
VSYN
PRELIMINARY DATA SHEET - Rev 1.3 12/2003
3
ACD2203
ELECTRICAL CHARACTERISTICS
Table 2: Absolute Minimum and Maximum Ratings
PARAMETER Supply Voltage (pins 25, 27 & 28) (pin 15) Voltage on pins 10 through 14, 16 through 19 with VSS = 0 V Input Voltages (pins 1, 2 & 5) Input Power (pins 1 & 2) (pin 5) (pins 13, 16 & 19)
MIN -0.3 -55 -
MAX +9 +6.5 VSYN +0.3 0 +10 +17 +20 +150 260 4 40
UNIT VD C VD C VD C dB m C C S ec C/W
Storage Temperature Soldering Temperature Soldering Time Thermal Impedance, JC
Stresses in excess of the absolute ratings may cause permanent damage. Functional operation is not implied under these conditions. Exposure to absolute ratings for extended periods of time may adversely affect reliability.
Table 3: Operating Ranges
PARAMETER Downconverter Frequencies RF Input (RF) IF Output (IF) Local Oscillator (LO)
(1)
MIN 900 35 865 400 400 2 +4.70 -40
TYP 4 +5 -
MAX 1200 150 1350 2100 1400 20 10 +5.25 +85
UNIT
MHz
Synthesizer Frequencies Upconverter Synthesizer (RFU) Downconverter Synthesizer (RFD) Reference Oscillator (REFIN) Phase Detector Supply Voltage: VDD (pins 15, 25, 27, 28) Ambient Operating Temperature: TA
(2)
MHz
VD C C
The device may be operated safely over these conditions; however, parametric performance is guaranteed only over the conditions defined in the electrical specifications. Notes: (1) Mixer operation is possible beyond these frequencies with slightly reduced performance. (2) Case Temperature is 15 C higher than Ambient Temperature, when Ambient Temperature is +25 C, using the PC Board Layout shown in Figures 24-26.
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PRELIMINARY DATA SHEET - Rev 1.3 12/2003
ACD2203 Table 4: Electrical Specifications - Downconverter Section (7) (TA = +25 C , VDD = +5 VDC, RFIN = 1087 MHz, IFOUT = 45 MHz)
PARAMETER Conversion Gain (1) Conversion Gain (2) SSB Noise Figure (2), (3) Cross Modulation (2), (4), (6) 3 Order Intermodulation Distortion (IMD3) (2), (5), (6)
rd
MIN 8 11 +12 -10 -
TYP 10 13 4 -56 -90 -5 -10 -48 -50 -10 50 30 400
MAX 14 17 7 -53 -53 -85.5 65 45 550
UNIT dB dB dB c dB c dB m dBc/Hz dB m dB m dB c dB m dB m mA mA mW
2-Tone 3rd Order Input Intercept Point (IIP3) (2), (5), (6) LO Phase Noise (@ 10 KHz Offset) (1), (2) LO Output Power (pin 24) (1), (2) Spurious @ IF Output LO Signals and Harmonics Beats Within Output Channel Other Beats from 2 to 200 MHz Other Spurious IF Supply Current (pin 27 & 28) (1), (2),(6) Osc/Phase Splitter Supply Current (pin 25) Power Consumption
Notes: (1) As measured in ANADIGICS test fixture with single-ended RF input. (2) As measured in ANADIGICS test fixture with differential RF inputs. (3) SSB noise figure will be approximately 3 dB higher with single-ended RF input. (4) Two tones: 1085 and 1091 MHz, -20 dBm each, 1091 MHz tone AM-modulated 99% at 15 kHz. (5) Two tones: 1085 and 1091 MHz, -15 dBm each. (6) R1 = 10 Ohms. (7) Case Temperature is 15 C higher than Ambient Temperature, when Ambient Temperature is +25 C, using the PC Board Layout shown in Figures 24-26.
PRELIMINARY DATA SHEET - Rev 1.3 12/2003
5
ACD2203 Table 5: Electrical Specifications - Synthesizer Section (4) (TA = +25 C , VDD = +5 VDC)
PARAMETER Prescalar Input Sensitivity Upconverter: RFU (pin 16) (1) Downconverter: RFD (pin 19) (2) Upconverter: RFU (pin 16) (1) Downconverter: RFD (pin 19) (2) Reference Oscillator Sensitivity (pin 13) Charge Pump Output Current (3) SINK SOURCE Supply Current Power Consumption MIN -7 -13 -6 -11 TYP 0.5 1.25 -1.25 35 165 MAX +20 +20 50 250 UNIT COMMENTS (over operating frequency) dB m TA = +85 C, VDD = +4.7 V TA = +85 C, VDD = +4.7 V Vp-p
mA mA mW
Notes: (1) Measured at 250 kHz comparison frequency. (2) Measured at 62.5 kHz comparison frequency. (3) CPU and CPD = VCC/2. (4) Case Temperature is 15 C higher than Ambient Temperature, when Ambient Temperature is +25 C, using the PC Board Layout shown in Figures 24-26.
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PRELIMINARY DATA SHEET - Rev 1.3 12/2003
ACD2203 Table 6: Digital 2-Wire Interface Specifications (TA = +25 C, VDD = +5 VDC, ref. Figure 4)
PARAMETER CLK Frequency Logic High Input (pins 11, 12) Logic Low Input (pins 11, 12) Logic Input Current Consumption (pins 11, 12) Address Select Input Current Consumption (pin 10) Data Sink Current (2) Bus Free Time between a STOP and START Condition Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. LOW period of CLK HIGH period of CLK Set-up Time for a Repeated START Condition Data Hold Time (for 2-wire bus devices) Data Set-up Time Rise Time of DATA and CLK Signals Fall Time of Data and CLK Signals Set-up Time for STOP Condition Capacitive Load for Each Bus Line
SYMBOL fCLK VH VL ILOG IAS IAK tBUF
MIN 1 2.0 1.3
MAX 400 0.8 10 10 4.0 -
UNIT kHz V V A A mA s
tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tR tF tSU;STO Cb
0.6 1.3 0.6 0.6 0.0 100 20 + 0.1Cb (1) 20 + 0.1Cb 0.6 (1)
0.9 300 300 400
s s s s s ns ns ns s pF
Notes: (1) Cb is the total capacitance of one bus line in pF. (2) For maximum 0.8 V level during Acknowledge Pulse. 3. All timing values are referred to minimum VH and maximum VL levels.
DATA tF CLK
S
tLOW
tR
tSU;DAT
tF
tHD;STA
tSP
tR
tBUF
tHD;STA
tHD;DAT
tHIGH
tSU;STA
Sr
tSU;STO
P
S
Figure 4: Serial 2-Wire Data Input Timing
PRELIMINARY DATA SHEET - Rev 1.3 12/2003
7
ACD2203
PERFORMANCE DATA
Figure 5: Typical Conversion Gain and Noise Figure vs. Supply Voltage (TA = +25 C, fLO2 = 1042 MHz)
14.0 3.65 13.8 3.63
Figure 6: Typical Conversion Gain and Noise Figure vs. Ambient Temperature (VDD = +5 V, fLO2 = 1042 MHz)
15.0 5.0 14.0 4.6
Conversion Gain (dB)
Conversion Gain (dB)
Noise Figure (dB)
13.6
3.61
13.0
4.2
13.4
3.59
12.0
3.8
13.2
Conversion Gain Noise Figure
3.57
11.0
Conversion Gain Noise Figure
3.4
13.0 4.7 4.8 4.9 5.0 5.1 5.2 5.3
3.55
10.0 25 35 45 55 65 75 85
3.0
Supply Voltage (V)
Ambient Temperature (C)
Figure 7: Typical Phase Noise at 10 kHz Offset vs. Supply Voltage (TA = +25 C, fLO2 = 1042 MHz)
-90 -91
Figure 8: Typical Phase Noise at 10 kHz Offset vs. Ambient Temperature (VDD = +5 V, fLO2 = 1042 MHz)
-84 -86
Phase Noise (dBc/Hz)
Phase Noise (dBc/Hz)
-92
-88
-93
-90
-94
-92
-95 4.7 4.8 4.9 5.0 5.1 5.2 5.3
-94 25 35 45 55 65 75 85
Supply Voltage (V)
Ambient Temperature (C)
Figure 9: Typical Local Oscillator Output Power vs. Supply Voltage (TA = +25 C, fLO2 = 1042 MHz)
-4.5 -5.0
Figure 10: Typical Local Oscillator Output Power vs. Ambient Temperature (VDD = +5 V, fLO2 = 1042 MHz)
-4.5 -5.0
Output Power (dBm)
Output Power (dBm)
-5.5
-5.5
-6.0
-6.0
-6.5
-6.5
-7.0 4.7 4.8 4.9 5.0 5.1 5.2 5.3
-7.0 25 35 45 55 65 75 85
Supply Voltage (V)
Ambient Temperature (C)
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PRELIMINARY DATA SHEET - Rev 1.3 12/2003
Noise Figure (dB)
ACD2203
Figure 11: Typical Upconverter Prescaler Sensitivity vs. Local Oscillator Frequency (TA = +25 C, VDD = +5 V)
-5
Figure 12: Typical Downconverter Prescaler Sensitivity vs. Local Oscillator Frequency (TA = +25 C, VDD = +5 V)
-12
Prescalar Sensitivity (dBm)
-15
Prescalar Sensitivity (dBm)
700 900 1100 1300 1500 1700 1900 2100
-10
-14
-16
-20
-18
-25
-20
-30
-22
-35 500
-24 400
600
800
1000
1200
1400
LO1 Frequency (MHz)
LO2 Frequency (MHz)
Figure 13: Typical Upconverter Prescaler Sensitivity vs. Supply Voltage (TA = +25 C, fLO1 = 2100 MHz)
-7.0
Figure 14: Typical Downconverter Prescaler Sensitivity vs. Supply Voltage (TA = +25 C, fLO2 = 1000 MHz)
-16.0
Prescalar Sensitivity (dBm)
Prescalar Sensitivity (dBm)
4.7 4.8 4.9 5.0 5.1 5.2 5.3
-7.5
-16.5
-8.0
-17.0
-8.5
-17.5
-9.0
-18.0 4.7 4.8 4.9 5.0 5.1 5.2 5.3
Supply Voltage (V)
Supply Voltage (V)
Figure 15: Typical Upconverter Prescaler Sensitivity vs. Ambient Temperature (VDD = +5 V, fLO1 = 2100 MHz)
-6.0
Figure 16: Typical Downconverter Prescaler Sensitivity vs. Ambient Temperature (VDD = +5 V, fLO2 = 1000 MHz)
-15.0
Prescalar Sensitivity (dBm)
-6.5
Prescalar Sensitivity (dBm)
-15.5
-7.0
-16.0
-7.5
-16.5
-8.0
-17.0
-8.5 25 35 45 55 65 75 85
-17.5 25 35 45 55 65 75 85
Ambient Temperature (C)
Ambient Temperature (C)
PRELIMINARY DATA SHEET - Rev 1.3 12/2003
9
ACD2203
Figure 17: Typical Conversion Gain and Noise Figure vs. LNA/Mixer Current Control Resistor R1 (TA = +25 C, VDD = +5 V, fLO2 = 1042 MHz)
15 5.0 14
C o n v e rs io n G a in (d B )
Figure 18: Typical Total Current Consumption vs. LNA/Mixer Current Control Resistor R1 (TA = +25 C, VDD = +5 V)
200 180
Conversion Gain Noise Figure
4.6
N o is e F ig u re (d B )
13
4.2
Current (mA)
160
140
12
3.8
120
11
3.4
100
10 0 5 10 15 20 25
3.0
80 0 5 10 15 20 25
R1 Resistor Value (W )
R1 Resistor Value (W )
Figure 19: Typical Input IP3 vs. LNA/Mixer Current Control Resistor R1 (TA = +25 C, VDD = +5 V)
19
-50
Figure 20: Typical Cross Modulation vs. LNA/Mixer Current Control Resistor R1 (TA = +25 C, VDD = +5 V)
Cross Modulation (dBc)
0 5 10 15 20 25
17
-55
IIP3 (dBm)
15
13
-60
11
9
-65 0 5 10 15 20
R1 Resistor Value (W )
R1 Resistor Value (W )
10
PRELIMINARY DATA SHEET - Rev 1.3 12/2003
ACD2203
LOGIC PROGRAMMING
The ACD2203 includes an interface for a two-wire serial data control bus that ANADIGICS has developed for use with its dual PLL synthesizers. This interface saves one connection between the host and the dual synthesizer, compared to a standard CLOCK-DATA-ENABLE three-wire interface. The interface is optimized for applications in which the dual synthesizer is a slave receiver device. Hosts that conform to the I 2 C-Bus Specification standard can be used to program a dual PLL that uses this interface. Physical Interface The two-wire interface consists of two digital signal lines, CLOCK and DATA. The speed of the interface is nominally 400 kbits/sec. For data transmission, the signal on the DATA line must be stable when the CLOCK signal is high, and the state of the data must change only while the CLOCK signal is low. A logic level transition on the DATA line during a high CLOCK signal indicates the beginning or end of a data transmission, as specified in the following sections and shown in Figure 21.
CLOCK
(10) decodes an analog voltage input into two digital logic output bits AS1 and AS2. The level of a DC voltage applied to this pin determines the two-bit logic state, AS2 and AS1 to address the synthesizer. The software must be programmed with the corresponding decimal equivalent of the 8b word selected, as shown in Table 7. Once the dual PLL has recognized the Start indicator and the correct address word, it sends an address acknowledgement to the host by pulling the DATA line low for one clock pulse. The host can then begin to send data to program the dual PLL. Sending Data After receiving the address byte acknowledgement from the dual PLL, the host begins sending programming data in 8-bit words. The MSB is sent first, and the LSB last. Following the receipt of each 8-bit data word, the dual PLL acknowledges receipt by pulling the DATA line low for one clock pulse. The data acknowledgement tells the host it may send the next data word. For the dual PLL, each group of three data words (24 bits total) is a significant block of information used to program one of four registers, as described in "Programming the Dual PLL." Completing Data Transmissions After sending the final data word, the host sends a Stop indicator to mark the end of data transmission. A Stop is indicated by a low-to-high transition of the DATA signal while the CLOCK signal is held high. After receiving the Stop indicator, the dual PLL ceases to send further acknowledgements and begins to monitor the CLOCK and DATA signals for the next Start indicator. Note: The Stop indicator does not directly control when the programming data is latched or takes effect; the data takes effect immediately following the receipt of each three-word block of data, which represents a complete 24-bit divider register. Resending Data If, for some reason, the data transmission fails or is interrupted, and the dual PLL fails to send an address word or data word acknowledgement to the host, the host can resend the data. To resend data, a new Start indicator and address word must be sent prior to any data words. Programming The Dual PLL Each synthesizer in the dual PLL contains programmable Reference and Main dividers, which 11
Start Indicator:
DATA
CLOCK
Stop Indicator:
DATA
Figure 21: Transmission Indicators Addressing The Dual PLL The dual PLL monitors the CLOCK and DATA signals for a Start indication from the host. A Start is indicated by a high-to-low transition of the DATA signal while the CLOCK signal is high. Immediately following the Start indicator, the host sends an 8-bit address word to the dual PLL. The 8-bit word required to address the dual PLL is programmable via a DC voltage level applied to the address select pin. For example, a voltage of 4VPRELIMINARY DATA SHEET - Rev 1.3 12/2003
ACD2203 Table 7: Address Select Decoding (TA = +25 C (1), VDD = +5 VDC)
VOLTAGE ON PIN 10, AS VSS < AS < 0.8V 1.1V < AS < 1.7V 2.1V < AS < 2.7V 3.15V < AS < 3.65V 4.2V < AS < VDD C (BINARY 12) B7 1 1 1 1 1 B6 1 1 1 1 1 B5 0 0 0 0 0 B4 0 0 0 0 0 B3 0 0 0 0 0 AS2 AS1 B2 0 0 1 0 1 B1 1 0 0 0 1 B0 0 0 0 0 0 H EX C2 C0 C4 C0 C6 DECIMAL 194 192 196 192 198
Notes: (1) Case Temperature is 15 C higher than Ambient Temperature, when Ambient Temperature is +25 C, using the PC Board Layout shown in Figures 24-26.
allow a wide range of output frequencies. The 24-bit registers that control the dividers and other functions are each segmented into three 8-bit data words, and are programmed via the two-wire interface. Register Select Bits The two least significant bits of each register are register select bits that determine which register is programmed during a particular data entry cycle. Table 8 indicates the register select bit settings used to program each of the available registers. Table 8: Register Select Bits
S E LE C T BITS S 2 0 0 1 1 S 1 0 1 0 1 DESTINATION REGISTER FOR SERIAL DATA
Main Divider Programming The main divider register for each synthesizer consists of seven A counter bits, eleven B counter bits, two program mode bits and the two register select bits, as shown in Table 11. The main divider divide ratio, N, is determined by the values in the A and B counters. The eleven B Counter bits and allowed values are shown in Table 12, and the seven A Counter bits and allowed values are shown in Table 13. Note that there are some limitations on the ranges of the values for each counter. Pulse Swallow Function The VCO output frequency for the local oscillator is computed using the following equation; the variables are defined in Table 14: fVCO = N x fOSC/R, where N = [(P x B) + A] where: N = [(P x B) + A] fVCO is the desired output frequency B is the divide ratio of the B counter (3 to 2047) A is the divide ratio of the A counter (0Reference Divider Register for PLL2 Main Divider Register for PLL2 Reference Divider Register for PLL1 Main Divider Register for PLL1
Reference Divider Programming The reference divider register for each synthesizer consists of fifteen divider bits, five program mode bits and the two register select bits, as shown in Table 9. The fifteen divider bits allow a divide ratio from 3 to 32767, inclusive, as shown in Table 10.
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PRELIMINARY DATA SHEET - Rev 1.3 12/2003
ACD2203
MSB
Table 9: Reference Divider Registers
FIRST DATA WORD SECOND DATA WORD
17 16 15 14 13 12 11 10 9 8
LSB
Data Word Register Bit Function Data
24
THIRD DATA WORD
7 6 5 4 3 2 1
23
22
21
20
19
18
Dummy/ S p a ce r
Program Mode
D 5 D 4 D 3 D 2 D 1 R 15 R 14 R 13 R 12
Reference Divider Divide Ratio, R
R 11 R 10 R 9 R 8 R 7 R 6 R 5 R 4 R 3 R 2 R 1
Select
S 2 S 1
X 2
X 1
Table 10: Reference Divider R Counter Bits
DIVIDE RATIO R 3 4 32767
R 15 0 0 1
R 14 0 0 1
R 13 0 0 1
R 12 0 0 1
R 11 0 0 1
R 10 0 0 1
R 9 0 0 1
R 8 0 0 1
R 7 0 0 1
R 6 0 0 1
R 5 0 0 1
R 4 0 0 1
R 3 0 1 1
R 2 1 0 1
R 1 1 0 1
Notes: Divide ratios less than 3 are prohibited.
MSB Data Word Register Bit Function Data
24
Table 11: Main Divider Registers LSB
FIRST DATA WORD
23 22 21 20 19 18 17 16
SECOND DATA WORD
15 14 13 12 11 10 9 8
THIRD DATA WORD
7 6 5 4 3 2 1
Dummy/ S p a ce r
Program Mode
B Counter
B 11 B 10 B 9 B 8 B 7 B 6 B 5 B 4 B 3 B 2 B 1 A 7 A 6
A Counter
A 5 A 4 A 3 A 2 A 1
Select
S 2 S 1
X 2
X 1
C 2
C 1
Table 12: Main Divider B Counter Bits
VALUE OF B COUNTER 3 4 2047 B 11 0 0 1 B 10 0 0 1 B 9 0 0 1 B 8 0 0 1 B 7 0 0 1 B 6 0 0 1 B 5 0 0 1 B 4 0 0 1 B 3 0 1 1 B 2 1 0 1 B 1 1 0 1
Notes: B > A, Divide ratios less than 3 are prohibited. PRELIMINARY DATA SHEET - Rev 1.3 12/2003
13
ACD2203 Table 13: Main Divider A Counter Bits Bit C1 in each main divider register sets the prescalar mode. Table 16 indicates the appropriate settings. (Currently, there is only one prescalar mode available for use.) Table 16: Prescalar Mode
VALUE OF A COUNTER 0 1 127
Notes: B > A, A < P
A 7 0 0 1
A 6 0 0 1
A 5 0 0 1
A 4 0 0 1
A 3 0 0 1
A 2 0 0 1
A 1 0 1 1
C 1 0 1
PRESCALAR MODE 64/65 (reserved for future use)
Table 14: Phase Detector Polarity Bit
S 2 0 1
S 1 0 0
D 1 PLL2 Phase Detector Polarity PLL1 Phase Detector Polarity
Bit C2 in the main divider registers, bits D2 through D5 in the reference divider registers, and bits X1 and X2 in all registers are reserved for future use, and have no current function. They can be set either high or low without affecting synthesizer performance.
Programmable Modes Each register contains bits set aside for programming different modes of operation in the synthesizers. Bit D1 in each reference divider register controls the phase detector polarity. Table 14 shows how this bit controls the polarity, and the correct setting is determined by using Table 15 and Figure 22. Table 15: Phase Detector Polarity Selection
D 1 0 1
POLARITY Negative Positive
VC O CHARACTERISTICS curve (2) curve (1)
(1)
VCO OUTPUT FREQUENCY
(2)
VCO INPUT VOLTAGE
Figure 22: VCO Characteristics 14
PRELIMINARY DATA SHEET - Rev 1.3 12/2003
ACD2203 Synthesizer Programming Example The following example for programming the two synthesizers in the dual PLL details the calculations used to determine the required value of each bit in all four registers: Requirements Desired CATV input channel: "HHH" - 499.25 MHz picture carrier (501 MHz digital channel center frequency) (Second) IF picture carrier output frequency: 45.75 MHz (44 MHz digital channel center frequency) First IF frequency: 1087.75 MHz (recommended) Phase detector comparison frequency for down converter (also tuning increment): 62.5 KHz Phase detector comparison frequency for up converter: 250 KHz Crystal reference oscillator frequency: 4 MHz Calculation of Reference Divider Values The value for each reference divider is calculated by dividing the reference oscillator frequency by the desired phase detector comparison frequency: R = fOSC / fPD For the down converter, the 4 MHz crystal oscillator frequency and the 62.5 KHz phase detector comparison frequency are used to yield RPLL2 = 4 MHz / 62.5 KHz = 64, and so the bit values for the down converter R counter are RPLL2 = 000000001000000. For the up converter, the 4 MHz crystal oscillator frequency and the 250 KHz phase detector comparison frequency are used to yield RPLL1 = 4 MHz / 250 KHz = 16, and so the bit values for the up converter R counter are RPLL1 = 000000000010000. Calculation of Main Divider Values The values for the A and B counters are determined by the desired VCO output frequency for the local oscillator and the phase detector comparison frequency: N = fVCO / f PD B = trunc(N / P) A = N - (B x P)
The down converter local oscillator frequency will be 1087.75 MHz - 45.75 MHz = 1042 MHz in this example. The main divider ratio for the down converter, then, is NPLL2 = 1042 MHz / 62.5 KHz = 16672. Since P = 64 in the ACD2203, BPLL2 = trunc(16672 / 64) = 260, and APLL2 = 16672 - (260 x 64) = 32. These results give bit values of BPLL2 = 00100000100 and APLL2 = 0100000 for the B and A counters. The up converter local oscillator frequency will be 499.25 MHz + 1087.75 MHz = 1587 MHz in this example. Therefore, NPLL1 = 1587 MHz / 250 KHz = 6348, BPLL1 = trunc(6348 / 64) = 99, and APLL1 = 6348 - (99 x 64) = 12. These results give bit values of BPLL1 = 00001100011 and APLL1 = 0001100 for the B and A counters. Phase Detector Polarity If the VCO for the up converter has a negative slope, the phase detector polarity for PLL1 should be negative, and D1PLL1 = 1. If the VCO for the down converter has a positive slope, the phase detector polarity for PLL2 should be positive, and D1PLL2 = 0. In summary, for this example, the four register programming words are shown in Tables 17 and 18 on the following page.
PRELIMINARY DATA SHEET - Rev 1.3 12/2003
15
ACD2203 Table 17: PLL1 and PLL2 Reference Divider Register Bits for Synthesizer Programming Example
MSB
LSB
Data Word Register Bit Function Data PLL2 PLL1
24
FIRST DATA WORD
23 22 21 20 19 18 17 16
SECOND DATA WORD
15 14 13 12 11 10 9 8
THIRD DATA WORD
7 6 5 4 3 2 1
Dummy/ S p a ce r
Program Mode
D 5 0 0 D 4 0 0 D 3 0 0 D 2 0 0 D 1 1 0 R 15 0 0 R 14 0 0 R 13 0 0 R 12 0 0
Reference Divider Divide Ratio, R
R 11 0 0 R 10 0 0 R 9 0 0 R 8 0 0 R 7 1 0 R 6 0 0 R 5 0 1 R 4 0 0 R 3 0 0 R 2 0 0 R 1 0 0
Select
S 2 0 1 S 1 0 0
X 2 0 0
X 1 0 0
MSB
Table 18: PLL1 and PLL2 Main Divider Register Bits for Synthesizer Programming Example
FIRST DATA WORD SECOND DATA WORD
17 16 15 14 13 12 11 10 9 8
LSB
Data Word Register Bit Function Data PLL2 PLL1
24
THIRD DATA WORD
7 6 5 4 3 2 1
23
22
21
20
19
18
Dummy/ S p a ce r
Program Mode
B Counter
B 11 0 0 B 10 0 0 B 9 1 0 B 8 0 0 B 7 0 1 B 6 0 1 B 5 0 0 B 4 0 0 B 3 1 0 B 2 0 1 B 1 0 1 A 7 0 0 A 6 1 0
A Counter
A 5 0 0 A 4 0 1 A 3 0 1 A 2 0 0 A 1 0 0
Select
S 2 0 1 S 1 1 1
X 2 0 0
X 1 0 0
C 2 0 0
C 1 0 0
16
PRELIMINARY DATA SHEET - Rev 1.3 12/2003
ACD2203
APPLICATION INFORMATION
VSYN 20 kW VSYN pins 16,19 AV~ -1000 VSS VSS pins 17,18
VSYN 200 W
pin 13 VSS VSYN pin 14 VSS
pin 1 pin 2 300 kW pin 4
5 kW GND
5 kW GND
VSUP 10 W 15 W 5W GND 10 pF OSCGND
pin 27 5 pF
pin 28 5 pF 5W GND
pin 24 pin 5
Figure 23: Equivalent Circuits
PRELIMINARY DATA SHEET - Rev 1.3 12/2003
17
ACD2203
Figure 24: PC Board Layout Top View
Figure 25: PC Board Layout Mid View
RF
RF
IF Balun AFC Out
4M Hz Xtal
ACD2203 J1 LO In
1
Figure 26: PC Board Layout Bottom View Table 19: J1 Header Pinout PIN 1 2 3 4 5 6 18 FUNCTION Clock Data Ground AS +5 VDC +30 VDC
PIN RF RF IF
Figure 27: Evaluation Fixture Table 20: Fixture Pinout
FUNCTION Downconverter RF Input Downconverter RF Input IF Output (Single Ended)
AFC Out To Upconverter Oscillator Tuning Circuit LO In Synthesizer RFU LO Input
PRELIMINARY DATA SHEET - Rev 1.3 12/2003
IF
L3
C24 DT1 C1
1 +5V
RF RF
C2
2
RFIN+ C21 C22 C23 RFINGND ISET TCKT OSCGND OSCGND VSS VSS AS DATA CLK REFIN REFOUT ACD2203 R8 L2 RFU 16 VSYN 15 R9 R10 C14 C13 C12 C11 C10 C9 CPD 18 CPU 17 RFD 19 C20 C17 R11 VSS 21 VSS 20 GND 22 GND 23 OSC OUT 24 C16 VSUP 25 GND 26 VIF + IFOUT- 27
VIF + IFOUT+ 28
R1
4 5
3
R13
+30V
J1
7
D1
6
C3
C18 Q1
C19
6
+30V
5 9 10
+5V
L1
8
4
X NC
3
address select voltage (see Table 7) AS
2
R3 R4
12 13 14 11
R12
AFCOUT LOIN
1
Figure 28: Evaluation Fixture Schematic
R6 R7 X1
+5V
PRELIMINARY DATA SHEET - Rev 1.3 12/2003
C7 C8
C5
C6
C15
ACD2203
19
ACD2203 Table 21: Evaluation Fixture Parts List
ITEM # C 1, C 2, C 20 C3 C 7, C 8 C 12 C9, C11, C 14, C 21, C 22 C 10, C 23 C 15, C 17 C 16 C 18 C 19 C 24 C 13 C 5, C 6 R8 R1 R3, R4 R12 R11 R7 R13 R10 R6, R9 L1 VALUE 100pF 5pF 30pF 220uF .1uF SIZE 0603 0603 0603 DESCRIPTION Chip-capacitor Chip-capacitor Chip-capacitor PART #
GRM39COG101J50V GRM39COG050C50V GRM39COG300J50V PCE2040CT-ND GRM39Y5V104Z16V
QTY
3
VENDOR Murata Murata Murata DIGI-KEY Murata
1 2 1
10V VA Capacitor Series 0603 Chip-capacitor
5
1000pF 4700pF 1uF .01uF 10uF 15pF 5600pF 33pF 51 10 2K 1K 2.7K 3K 22K 8.2K 0 6.8nH
0603 0603 0603 0603 35 V TANT 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0805
Chip-capacitor Chip-capacitor Radial-lead Chip-capacitor Chip-capacitor
GRM39X7R102K50V GRM39X7R472K25V RPE113-X7R-105-K-050 GRM39X7R103K25V
2 2 1
Murata Murata Murata Murata DIGI-KEY Murata Murata Murata Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic RCD Coilcraft
1 1
TE Series Cap. PCS6106CT-ND Chip-capacitor Chip-capacitor Chip-capacitor Chip Resistor Chip Resistor Chip Resistor Chip Resistor Chip Resistor Chip Resistor Chip Resistor Chip Resistor Chip Resistor Inductor
GRM39COG150J50V GRM39X7R562K50V GRM39COG330J50V ERJ-3GSYJ510 ERJ-3GSYJ100 ERJ-3GSYJ202 ERJ-3GSYJ102 ERJ-3GSYJ272 ERJ-3GSYJ302 ERJ-3GSYJ223 ERJ-3GSYJ822 ZC0603 0805CS-060X-BC
1 1 2 1 1 2 1 1 1 1 1 2 1
20
PRELIMINARY DATA SHEET - Rev 1.3 12/2003
ACD2203 Table 21: Evaluation Fixture Parts List continued
ITEM # L2 L3 D1 DT1 Q1 X1
VALUE 68nH 270nH 1S V 245 4:1 30V SMD 4MHZ
SIZE 0805 0805
DESCRIPTION Inductor Inductor Varactor diode Transformer
PART #
0805CS-680X-BC 0805CS-271X-BC 1SV245 ETC4-1-2 FMMTA13CT-ND SE2618CT-ND
QTY
1 1 1 1
VENDOR Coilcraft Coilcraft Toshiba M/A-COM, Inc. North America DIGI-KEY DIGI-KEY
SOT-23
Transistor NPN Darl. Crystal
1
1
PRELIMINARY DATA SHEET - Rev 1.3 12/2003
21
ACD2203
PACKAGE OUTLINE
Figure 29: S8 Package Outline - 28 Pin SSOP
22
PRELIMINARY DATA SHEET - Rev 1.3 12/2003
ACD2203
NOTES
PRELIMINARY DATA SHEET - Rev 1.3 12/2003
23
ACD2203
ORDERING INFORMATION
ORDER NUMBER A C D 2203S 8P 1 A C D 2203S 8P 0 ACD2203S8GP1 ACD2203S8GP0 TEMPERATURE RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PACKAGE DESCRIPTION 28 Pin SSOP 28 Pin SSOP Lead-free 28 Pin SSOP Lead-free 28 Pin SSOP COMPONENT PACKAGING Tape & Reel, 3500 pieces per reel Tubes, 50 pieces per tube Tape & Reel, 3500 pieces per reel Tubes, 50 pieces per tube
ANADIGICS, Inc. 141 Mount Bethel Road Warren, New Jersey 07059, U.S.A Tel: +1 (908) 668-5000 Fax: +1 (908) 668-5132 URL: http://www.anadigics.com E-mail: Mktg@anadigics.com
IMPORTANT NOTICE ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without notice. The product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets are subject to change prior to a product's formal introduction. Information in Data Sheets have been carefully checked and are assumed to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges customers to verify that the information they are using is current before placing orders. WARNING ANADIGICS products are not intended for use in life support appliances, devices, or systems. Use of an ANADIGICS product in any such application without written consent is prohibited.
24
PRELIMINARY DATA SHEET - Rev 1.3 12/2003

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